? semiconductor components industries, llc, 2014 august, 2014 ? rev. 7 1 publication order number: mc74hc390a/d mc74hc390a dual 4-stage binary ripple counter with 2 and 5 sections high?performance silicon?gate cmos the mc74hc390a is identical in pinout to the ls390. the device inputs are compatible with standard cmos outputs; with pullup resistors, they are compatible with lsttl outputs. this device consists of two independent 4?bit counters, each composed of a divide?by?two and a divide?by?five section. the divide?by?two and divide?by?five counters have separate clock inputs, and can be cascaded to implement various combinations of 2 and/or 5 up to a 100 counter. flip?flops internal to the counters are triggered by high?to?low transitions of the clock input. a separate, asynchronous reset is provided for each 4?bit counter. state changes of the q outputs do not occur simultaneously because of internal ripple delays. therefore, decoded output signals are subject to decoding spikes and should not be used as clocks or strobes except when gated with the clock of the hc390a. features ? output drive capability: 10 lsttl loads ? outputs directly interface to cmos, nmos, and ttl ? operating voltage range: 2.0 to 6.0 v ? low input current: 1 a ? high noise immunity characteristic of cmos devices ? in compliance with the requirements defined by jedec standard no 7 a ? chip complexity: 244 fets or 61 equivalent gates ? nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable ? these devices are pb?free, halogen free/bfr free and are rohs compliant q a q b q c q d 1, 15 4, 12 2, 14 3, 13 5, 11 6, 10 7, 9 pin 16 = v cc pin 8 = gnd clock a reset clock b 2 counter 5 counter figure 1. logic diagram http://onsemi.com see detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. ordering information marking diagrams soic?16 d suffix case 751b tssop?16 dt suffix case 948f 1 16 hc390ag awlyww hc 390a alyw 1 16 a = assembly location l, wl = wafer lot y, yy = year w, ww = work week g or = pb?free package (note: microdot may be in either location) soic?16 tssop?16 function table clock a b reset action x x h reset 2 and 5 x l increment 2 x l increment 5 pin assignment 13 14 15 16 9 10 11 12 5 4 3 2 1 8 7 6 clock b b q ab reset b clock a b v cc q db q cb q bb clock b a q aa reset a clock a a gnd q da q ca q ba
mc74hc390a http://onsemi.com 2 ??????????????????????? ??????????????????????? ???? ???? ?????????????? ?????????????? ????? ????? ??? ??? ???? ???? v cc ?????????????? ?????????????? ????? ????? ??? ??? ???? ???? ?????????????? ?????????????? ????? ????? ??? ??? ???? ?????????????? ????? ??? ???? ???? ?????????????? ?????????????? ????? ????? 20 ??? ??? ???? ???? ?????????????? ?????????????? ????? ????? 25 ??? ??? ???? ???? ?????????????? ?????????????? ????? ????? 50 ??? ??? ???? ???? ???? ?????????????? ?????????????? ?????????????? ????? ????? ????? ??? ??? ??? ???? ???? ?????????????? ?????????????? ????? ????? ??? ??? c ???? ???? ???? ?????????????? ?????????????? ?????????????? ????? ????? ????? ??? ??? ??? c stresses exceeding those listed in the maximum ratings table may damage the device. if any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. ?derating: soic package: ?7 mw/ c from 65 to 125 c tssop package: ?6.1 mw/ c from 65 to 125 c recommended operating conditions symbol parameter min max unit v cc dc supply voltage (referenced to gnd) 2.0 6.0 v v in , v out dc input voltage, output voltage (referenced to gnd) 0 v cc v t a operating temperature, all package types ?55 +125 c t r , t f input rise and fall time v cc = 2.0 v (figure 1) v cc = 3.0 v v cc = 4.5 v v cc = 6.0 v 0 0 0 0 1000 600 500 400 ns functional operation above the stresses listed in the recommended operating ranges is not implied. extended exposure to stresse s beyond the recommended operating ranges limits may affect device reliability. dc electrical characteristics (voltages referenced to gnd) symbol parameter test conditions v cc v guaranteed limit unit ?55 to 25 c 85 c 125 c v ih minimum high?level input voltage v out = 0.1 v or v cc ? 0.1 v |i out | 20 a 2.0 3.0 4.5 6.0 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 1.5 2.1 3.15 4.2 v v il maximum low?level input voltage v out = 0.1 v or v cc ? 0.1 v |i out | 20 a 2.0 3.0 4.5 6.0 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 0.5 0.9 1.35 1.8 v v oh minimum high?level output voltage v in = v ih or v il |i out | 20 a 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 v v in = v ih or v il |i out | 2.4 ma |i out | 4.0 ma |i out | 5.2 ma 3.0 4.5 6.0 2.48 3.98 5.48 2.34 3.84 5.34 2.20 3.70 5.20 v ol maximum low?level output voltage v in = v ih or v il |i out | 20 a 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 v v in = v ih or v il |i out | 2.4 ma |i out | 4.0 ma |i out | 5.2 ma 3.0 4.5 6.0 0.26 0.26 0.26 0.33 0.33 0.33 0.40 0.40 0.40 this device contains protection circuitry to guard against damage due to high static voltages or electric fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance cir- cuit. for proper operation, v in and v out should be constrained to the range gnd (v in or v out ) v cc . unused inputs must always be tied to an appropriate logic voltage level (e.g., either gnd or v cc ). unused outputs must be left open.
mc74hc390a http://onsemi.com 3 dc electrical characteristics (voltages referenced to gnd) (continued) symbol unit guaranteed limit v cc v test conditions parameter symbol unit 125 c 85 c ?55 to 25 c v cc v test conditions parameter i in maximum input leakage current v in = v cc or gnd 6.0 0.1 1.0 1.0 a i cc maximum quiescent supply current (per package) v in = v cc or gnd i out = 0 a 6.0 4 40 160 a ac electrical characteristics (c l = 50 pf, input t f = t f = 6 ns) symbol parameter v cc v guaranteed limit unit ?55 to 25 c 85 c 125 c f max maximum clock frequency (50% duty cycle) (figures 1 and 3) 2.0 3.0 4.5 6.0 10 15 30 50 9 14 28 45 8 12 25 40 mhz t plh , t phl maximum propagation delay, clock a to qa (figures 1 and 3) 2.0 3.0 4.5 6.0 70 40 24 20 80 45 30 26 90 50 36 31 ns t plh , t phl maximum propagation delay, clock a to qc (qa connected to clock b) (figures 1 and 3) 2.0 3.0 4.5 6.0 200 160 58 49 250 185 65 62 300 210 70 68 ns t plh , t phl maximum propagation delay, clock b to qb (figures 1 and 3) 2.0 3.0 4.5 6.0 70 40 26 22 80 45 33 28 90 50 39 33 ns t plh , t phl maximum propagation delay, clock b to qc (figures 1 and 3) 2.0 3.0 4.5 6.0 90 56 37 31 105 70 46 39 180 100 56 48 ns t plh , t phl maximum propagation delay, clock b to qd (figures 1 and 3) 2.0 3.0 4.5 6.0 70 40 26 22 80 45 33 28 90 50 39 33 ns t phl maximum propagation delay, reset to any q (figures 2 and 3) 2.0 3.0 4.5 6.0 80 48 30 26 95 65 38 33 110 75 44 39 ns t tlh , t thl maximum output transition time, any output (figures 1 and 3) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 15 110 36 22 19 ns c in maximum input capacitance ? 10 10 10 pf c pd power dissipation capacitance (per counter)* typical @ 25 c, v cc = 5.0 v pf 35 * used to determine the no?load dynamic power consumption: p d = c pd v cc 2 f + i cc v cc .
mc74hc390a http://onsemi.com 4 timing requirements (input t r = t f = 6 ns) symbol parameter v cc v guaranteed limit unit ?55 to 25 c 85 c 125 c t rec minimum recovery time, reset inactive to clock a or clock b (figure 3) 2.0 3.0 4.5 6.0 25 15 10 9 30 20 13 11 40 30 15 13 ns t w minimum pulse width, clock a, clock b (figure 2) 2.0 3.0 4.5 6.0 75 27 15 13 95 32 19 15 110 36 22 19 ns t w minimum pulse width, reset (figure 3) 2.0 3.0 4.5 6.0 75 27 20 18 95 32 24 22 110 36 30 28 ns t f , t f maximum input rise and fall times (figure 2) 2.0 3.0 4.5 6.0 1000 800 500 400 1000 800 500 400 1000 800 500 400 ns pin descriptions inputs clock a (pins 1, 15) and clock b (pins 4, 15) clock a is the clock input to the 2 counter; clock b is the clock input to the 5 counter. the internal flip?flops are toggled by high?to?low transitions of the clock input. control inputs reset (pins 2, 14) asynchronous reset. a high at the reset input prevents counting, resets the internal flip?flops, and forces q a through q d low. outputs q a (pins 3, 13) output of the 2 counter. q b , q c , q d (pins 5, 6, 7, 9, 10, 11) outputs of the 5 counter. q d is the most significant bit. q a is the least significant bit when the counter is connected for bcd output as in figure 5. q b is the least significant bit when the counter is operating in the bi?quinary mode as in figure 6. switching waveforms q t r t f t plh t phl t tlh t thl v cc gnd clock 10% 50% 90% 1/f max t w t rec reset figure 2. v cc gnd v cc gnd 10% 50% 90% q clock 50% 50% 50% t phl t w 10% figure 3.
mc74hc390a http://onsemi.com 5 c d r q q 0123456789 expanded logic diagram timing diagram (q a connected to clock b) q a q b q c q d clock a reset q a q b q c q d clock a clock b reset 3, 13 5, 11 6, 10 7, 9 1, 15 4, 12 2, 14 c d r q q c d r q q c d r q 0123456 test circuit *includes all probe and jig capacitance c l * test point device under test output figure 4.
mc74hc390a http://onsemi.com 6 applications information each half of the mc54/74hc390a has independent 2 and 5 sections (except for the reset function). the 2 and 5 counters can be connected to give bcd or bi?quinary (2?5) count sequences. if output q a is connected to the clock b input (figure 4), a decade divider with bcd output is obtained. the function table for the bcd count sequence is given in table 1. to obtain a bi?quinary count sequence, the input signals connected to the clock b input, and output q d is connected to the clock a input (figure 6). q a provides a 50% duty cycle output. the bi?quinary count sequence function table is given in table 2. table 1. bcd count sequence* count output q d q c q b q a 0 l l l l 1 l l l h 2 l l h l 3 l l h h 4 l h l l 5 l h l h 6 l h h l 7 l h h h 8 h l l l 9 h l l h *q a connected to clock b input. table 2. bi?quinary count sequence** count output q a q d q c q b 0 l l l l 1 l l l h 2 l l h l 3 l l h h 4 l h l l 8 h l l l 9 h l l h 10 h l h l 11 h l h h 12 h h l l ** q d connected to clock a input. connection diagrams 1, 15 2 counter clock a reset figure 5. bcd count figure 6. bi-quinary count 2 counter 5 counter 5 counter clock b clock a reset clock b 1, 15 q a q b q c q d 3, 13 5, 11 6, 10 7, 9 4, 12 2, 14 q a q b q c q d 3, 13 5, 11 6, 10 7, 9 4, 12 2, 14 ordering information device package shipping ? MC74HC390ADG soic?16 (pb?free) 48 units / rail mc74hc390adr2g soic?16 (pb?free) 2500 / tape & reel mc74hc390adtr2g tssop?16 (pb?free) 2500 / tape & reel nlv74hc390adr2g* soic?16 (pb?free) 2500 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d. *nlv prefix for automotive and other applications requiring unique site and control change requirements; aec?q100 qualified and ppap capable
mc74hc390a http://onsemi.com 7 package dimensions tssop?16 case 948f issue b ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c ??? 1.20 ??? 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane ?w?. section n?n seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) ?t? ?v? ?w? 0.25 (0.010) 16x ref k n n 7.06 16x 0.36 16x 1.26 0.65 dimensions: millimeters 1 pitch soldering footprint* *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d.
mc74hc390a http://onsemi.com 8 package dimensions soic?16 case 751b?05 issue k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ?b? ?a? m 0.25 (0.010) b s ?t? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 6.40 16x 0.58 16x 1.12 1.27 dimensions: millimeters 1 pitch soldering footprint* 16 89 8x *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. on semiconductor and the are registered trademarks of semiconductor components industries, llc (scillc) or its subsidia ries in the united states and/or other countries. scillc owns the rights to a number of pa tents, trademarks, copyrights, trade secret s, and other intellectual property. a listin g of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent?marking.pdf. scillc reserves the right to make changes without further notice to any product s herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any part icular purpose, nor does sci llc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typi cal? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating param eters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgic al implant into the body, or other applications intended to s upport or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemni fy and hold scillc and its officers, em ployees, subsidiaries, affiliates, and dist ributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufac ture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. p ublication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5817?1050 mc74hc390a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loc al sales representative
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